Edge intelligence,
engineered.
We don't chase the future. We build what it runs on. Ultra-low-power accelerator IP for the intelligent machines of tomorrow — local inference, zero round-trip.
The substrate beneath intelligence.
Built for power-constrained inference, from day one.
VDOTX designs ultra-low-power edge AI compute architecture — accelerator IP and silicon platforms that let intelligent machines run inference locally. Lower power. Lower latency. Better privacy. No cloud round-trip.
VDOTX is not an AI software layer. It is the compute foundation underneath. That distinction shapes every choice we make.
Read our position →Precision. Efficiency. Inference, where it happens.
Ternary crossbar core with multi-precision routing.
Our compiler and compute fabric are being co-designed for edge environments. The architecture routes mathematical operations through a ternary crossbar array with the goal of predictable latency and high energy efficiency.
The current design targets local inference, low-latency response, and sub-watt operating envelopes. Performance claims remain subject to FPGA and silicon validation.
Ternary crossbar fabric
A routed compute substrate built for edge inference — multi-precision, deterministic, power-aware from the first transistor.
Performance per watt, by design
Dynamic precision routing matches workloads to suitable hardware blocks. We evaluate results across representative workloads, latency, and wall power, with TOPS as one measure among several.
Fault-tolerant compute
Planned error handling and structural redundancy for constrained environments, to be qualified during prototype and silicon validation.
Edge-first, not edge-adapted.
- FoundationArchitecture & IP development. Define the compute fabric, compiler interface, and validation plan.
- Current target · 2026FPGA bring-up. Demonstrate end-to-end inference on representative workloads and publish measured results.
- NextDesign-partner validation. Align workloads, interfaces, and commercial requirements with selected hardware partners.
- Target · 2027Prototype silicon. Tape out a pilot design and characterize it against the published validation envelope.
Dates are current internal targets. Subject to design-partner alignment.
Foundational, not flashy.
Investors, licensees, integrators: come build the substrate the edge will run on.
Connect with engineering